Deep Trench Metrology Challenges for 75nm DRAM Technology

The demand for new DRAM technologies with smaller ground rules leads to new challenges for inline metrology. This paper addresses inline monitoring of structural dimensions like depths and critical dimension (CD), excluding defect density monitoring and advanced process control techniques. Qimonda pursues the deep trench (DT) capacitor concept A main module in DRAM manufacturing comprises DT etch, capacity enhancing steps, and the connection of the DT to the device. Interesting demands for metrology emerge with every new technology node. Focusing on 75nm DRAM technology, this paper will highlight key processes in the DT module. First, the mask process for DT etching requires measuring the bottom CD and the profile of structures with an aspect ratio in the order of 20: l. Upon DT main etch, profile determination like trench depth and bottom widening are needed. Thereafter, the DT capacity is increased by widening the trench below 1μm depth. To protect the upper area of the trench from being etched, a thin sacrificial layer is deposited on the DT sidewalls. Poly silicon grains are deposited for additional capacity improvement. Characterization of this layer inside the trench supports additional process monitoring. The deposition of the capacitor dielectric is followed by a sequence of poly silicon fills and poly recesses. The measurements of the shallow poly recess 2 and 3 depths are demanding applications at the end of the DT module. Possible metrology solutions will be discussed in this paper. Various measurement methods like scatterometry, wafer mass measurement, modelbased IR spectroscopy.and atomic force microscopy enable reliable process control which is indispensible for high volume production. Current 75nm DT-related processes can be monitored in a satisfactory way. Nevertheless, novel measurement capabilities that have not yet been fully explored will optimize process monitoring in the future. The performance and density requirements for future high-speed DRAM products lead to new challenges in both wafer processing and process monitoring. The 75nnl DRAM deep trench technology platform features minimum structure sizes down to 70nm. In addition to common metrology methods like ellipsometry, spectroscopy, and scanning electron ~microscopy (SEM), the use of further measurement techniques is mandatory for the trench capacitor concept. Scatterometry enables structure control by analyzing the light reflected from a structured surface. Wafer mass determination by a scale is employed to identify mass differences of the wafer at several steps in the process flow. Model-based reflectometry in the mid-infrared wavelength range allows access to detailed information on high-aspect ratio structures, even from depths several microns below the wafer surface. Atomic force microscopes using small diameter post shaped tips render geometry data of the possible shallow structures. In DT technology, the charge storage capacitor is formed by etching a deep highaspect ratio cavity into the silicon substrate using thick silicon oxide hardmask. The bottom dimension of this hardmask is the result of a sequence of resist structuring and nitride, amorphous silicon, and oxide hardmask opening steps (Figure 1). Direct measurement of this deep trench mask open (DTMO) bottom dimension allows both feed back control of the mask-open etch process sequence and feedforward control of the DT main etch. The metrology challenges arc the high aspect ratio of the hard mask, the remaining amorphous silicon hardmask profile as well as profile variations within the oxide mask. Conventional critical dimension scanning electron microscopy (CD SEM) measurements do not show reasonable correlation to the final top dimension of the DT as the CD SEM signa1 at DTMO is dominated by the upper regions of the hardmask. A modified CD SEM approach like "high aspect ratio contact bottom imaging” [1] provides information on the bottom dimension; however it requires sophisticated control of the surface charging. Fig.1 Deep trench mask open structure An alternative CD measurement method is scatterometry. In principle, this optical, modelbased technique is capable of providing the complete profile dimensions of line/space patterns (2D) or contact hole patterns (3D). However, the performance of scatterometry applications strongly depends on the specific application. The sensitivity to a parameter of interest is related to such factors as pitch, layer materials, stack, and profile complexity. Thus, even with sufficient parameter sensitivity, the measurement of a parameter may be affected by correlation to other model parameters. In this case a feedforward of results from earlier measurements reduces the complexity and may even improve the sensitivity to certain parameters [2]. The scatterometry measurement of the DTMO structure was investigated already in the 90nm DRAM technology [3]. The 75nm application is comparable, apart from the increased aspect ratio rid the smaller pitch. A specific challenge in the DTMO scatterometry application is the remaining amorphous silicon hardmask on top of the thick oxide. Because of its strong effect on the spectral response of the DTMO structure, the profile of this "high-index" material needs to be modeled in detail. When measured after removal of this remaining amorphous silicon hardmask, the complexity of the scatterometry application is reduced, but at the cost of a longer feed-back loop. An alternative option to a feed-back process control based on a direct DTMO measurement is a feed-forward process control based on the measurement after the amorphous silicon mask open which is a "straight forward" application with moderate aspect ratio and low profile complexity. After the trench main etch (Figure 2), there is a high demand for characterizing the DT cavities in terms of the total trench depth and trench dimensions at various vertical distances from the wafer surface. A further goal is to have an efficient line excursion monitoring for deviations from the ideal straight trench profile. Fouriertransformed infrared reflectometry (FTIR) has already proven to be a suitable inline metrology method for efficient non destructive control of DT-related process [4]. FTIR employs wavelengths in the range 1-10μm, i.e., much larger than the DRAM array pitch. As a result, light scattering is minimized and trench structures can be modeled as multilayered film stacks with optical properties of the various layers computed according to effective medium approximations. As silicon based microstructures are virtually transparent in this wavelength range, the infrared light beam penetrates the entire structure and generates an interference pattern associated with reflections from different interfaces along with the high-aspect ratio structures. Valuable information from the different trench depths is thus encoded in the measured infrared signal and can be extracted using model-based analysis algorithms, provided that optical contrast changes at the interfaces are sufficiently abrupt. Gradual changes in the profile, however, cannot be accessed by FTIR. Figure 3 depicts a typical FTIR spectrum of a DT structure taken at a 45° angle of incidence. The oscillation frequency depends on the depth and the mean void fraction of the structure. The Fig.2 Deep trench structure after main etch overall reflectivity level is related to the trench top widening because increasing top void fraction lowers the optical contrast between air and the top of the sample, thus lowering reflectivity. The bottom trench widening is correlated to the amplitude of the oscillation, since an increase in bottom void fraction increases the optical contrast at the trench/substrate interface. Fig.3 Typical experimental FTIR spectrum of the DT structure after main etch Employing an appropriate film stack model, the FTIR method has sufficient sensitivity to enable reliable determination of the trench depth and details of complex trench profiles, like the void fraction of the nitride/silicon interface and near the bottom of the trench. From the void fraction an effective, isotropically averaged CD can be derived. When comparing this parameter to CD values obtained from SEM top-down or cross section images, it has to be considered that the long and short axis CD of the trench actually do not have a fixed correlation to each other. Extracting trench dimension data from intermediate depths (e.g. at 3μm) by FTIR remains difficult. Thus, wafer mass measurements are employed to provide additional information on the average DT volume. To achieve sufficient capacity, the DT is widened by wet etch process. The widening should take place below a certain depth only, dividing the DT in an upper "neck" and a lower "bottle" part. To protect the upper part of the DT against the wet etch, a thin liner is deposited on the trench sidewalls in a self limiting process. The liner depth is routinely controlled using FTIR [4]. This is done after the wet etch process preventing the wafer from being reworked if the specification range was not met. Hence precise control of the liner deposition prior to etching would be beneficial. FTIR cannot be used, because the vertical reflective index contrast caused by the liner is too small. Screening for capable metrology methods has begun. In order to further improve the trench capacity, hemispherical grain (HSG) silicon is deposited on the trench sidewalls. The control of this deposition process is currently based on spectral ellipsometry measurements of unpatterned test wafers. An effective medium model provides HSG layer thickness as well as void fraction. The HSG growth is sensitive to the underlying material; however, there is reasonable correlation between the HSG growth inside the DT and on the test wafers. Nevertheless, on-product characterization of the HSG layer inside the trench is of high interest and a real metrology challenge. For determination of the total HSG volume in the trench, the FTIR method may provide useful local information. Weighing the wafer would be a fast measurement alternative, but is without lateral resolution. Furthermore, grains on the top wafer surface influence the scale measurement result. After HSG deposition, the grains are etched back to a level below the depth where the where the trench has been widened before (see Figure 4). On the one hand, grain residues in the trench neck act as yield detractors; on the other hand, trench capacity is diminished if the recess is set too deep. Thus, direct inline control of the recess depth is highly desirable. An FTIR analysis is hampered by the low optical contrast of the adjacent neck-bottle interface. Residuals in the neck and trench-to-trench variations of the recess depth further lead to additional attenuation of the respective FTIR signal component. If highly precise FTIR data acquired in an extended Fig.4 DT Structure